Efficient cache oblivious algorithms for randomized divide-and-conquer on the multicore model

In this paper we present randomized algorithms for sorting and convex hull that achieves optimal performance (for speed-up and cache misses) on the multicore model with private cache model. Our algorithms are cache oblivious and generalize the randomized divide and conquer strategy given by Reischuk [14] and Reif and Sen [17]. Although the approach yielded optimal speed-up in the PRAM model, we require additional techniques to optimize cache-misses in an oblivious setting. Let p, n,M,B respectively denote number of processors, problem size, the size of individual processor cache memory and block size respectively, then we obtain expected parallel running time O(np log n + log n log log n) with expected O( n B logM n) cache misses for sorting n keys and constructing convex hull of n points. For p ≤ n log logn , and under the tall-cache assumption M ≥ B , both speed-up and cache-misses are the best possible. Since the input-size n ≥ Mp, under a very mild assumption M ≥ log log n, p ≤ n log logn , so in all realistic scenarios, our algorithm will have optimal time and cache misses with high probability. Although similar results have been obtained recently for sorting [11] , we feel that our approach is simpler and general and we apply it to obtain an algorithm for 3D convex hulls with similar bounds. We also present a simple randomized processor allocation technique without the explicit knowledge of the number of processors that is likely to find additional applications in resource oblivious environments. SPAA’12, June 25–27, 2012, Pittsburgh, Pennsylvania, USA. 1 ar X iv :1 20 4. 65 08 v2 [ cs .D S] 2 7 M ay 2 01 2